Index: /branches/rel_apv_10_7/usr/click/bin/Makefile =================================================================== --- /branches/rel_apv_10_7/usr/click/bin/Makefile (revision 37953) +++ /branches/rel_apv_10_7/usr/click/bin/Makefile (working copy) @@ -80,7 +80,8 @@ aewin_cb1727 \ aewin_cb1939 \ led_screen \ - caswell_car3080 + caswell_car3080 \ + aewin_cb1920 .else SUBDIR= aaad \ sessmgrd \ Index: /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/ESDKerr.h =================================================================== --- /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/ESDKerr.h (revision 0) +++ /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/ESDKerr.h (working copy) @@ -0,0 +1,73 @@ + +// File error. +#define ERR_OPEN_FILE -1 +#define ERR_READ_FILE -2 +#define ERR_BOARD_TABLE -3 +#define ERR_DEVICE_TABLE -4 + +// Windows error +#define ERR_LOAD_FINTEK -10 +#define ERR_GET_FINTEK_FUNCTION -11 + +#define ERR_NO_SMBUS_DEVICE -50 + +// GPIO error. +#define ERR_GPIO_INDEX -100 +#define ERR_GPIO_SMBUS_NO_DEVICE -110 +#define ERR_GPIO_REGISTER -130 + +#define ERR_WDT_INDEX -200 + +#define ERR_FAN_INDEX -300 +#define ERR_FAN_SMBUS_NO_DEVICE -310 +#define ERR_FAN_VALUE -320 + +#define ERR_BUZZER_INDEX -400 + +#define ERR_BKLIGHT_INDEX -500 + +#define ERR_TEM_INDEX -600 +#define ERR_TEM_SMBUS_NO_DEVICE -610 +#define ERR_TEM_VALUE -620 + +#define ERR_VOLTAGE_INDEX -700 +#define ERR_VOLTAGE_SMBUS_NO_DEVICE -710 +#define ERR_VOLTAGE_VALUE -720 + +#define ERR_IPMISW_INDEX -800 + +#define ERR_SLOT_INDEX -900 + +#define ERR_BYPASS_INDEX -1000 +#define ERR_BYPASS_CODE -1001 +#define ERR_MCU_NO_DEVICE -1010 +#define ERR_MCU_BYPASS_VALUE -1020 +#define ERR_MCU_BYPASS_CODE -1021 +#define ERR_MCU_BYPASS_PAIR -1022 +#define ERR_MCU_BYPASS_TIME -1023 + +#define ERR_NetCard_EEPROM_INDEX -1100 +#define ERR_NetCard_EEPROM_NO_DEVICE -1110 +#define ERR_NetCard_EEPROM_BYPASS_VALUE -1120 +#define ERR_NetCard_EEPROM_BYPASS_CODE -1121 +#define ERR_NetCard_EEPROM_BYPASS_PAIR -1122 +#define ERR_NetCard_EEPROM_BYPASS_TIME -1123 +#define ERR_NetCard_EEPROM_BYPASS_INDEX -1124 +#define ERR_NetCard_EEPROM_BYPASS_OPTION -1125 +#define ERR_NetCard_EEPROM_MODULE_NAME -1126 + +#define ERR_EEPROM_INDEX -1200 +#define ERR_EEPROM_NO_DEVICE -1210 + +#define ERR_M1R2_G_INDEX -1300 +#define ERR_M1R2_G_NO_DEVICE -1310 + +#define ERR_LCMKEYPAD_INDEX -1300 +#define ERR_LCMKEYPAD_NO_DEVICE -1310 +#define ERR_LCMKEYPAD_NO_DETECT -1320 + +#define ERR_PSU_INDEX -1400 +#define ERR_PSU_NO_DEVICE -1410 +#define ERR_PSU_FAN_VALUE -1420 +#define ERR_PSU_TEMP_VALUE -1421 +#define ERR_PSU_VOLTAGE_VALUE -1422 Index: /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/gpio.c =================================================================== --- /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/gpio.c (revision 0) +++ /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/gpio.c (working copy) @@ -0,0 +1,1758 @@ +// ***********************************************// +// AEWIN GPIO Sample Code +// Version No : 1.3.0 +// ***********************************************// +#include +#include +#include +#ifdef __linux +#include +#else +#include +#endif +#include "ESDKerr.h" + +#ifdef __linux +void delay(int secs) +{ + usleep(secs * 1000); +} + +void outportl(unsigned long ulport, int data) +{ + outl(data, ulport); +} + +int inportl(unsigned long ulport) +{ + int data_rw32 = 0; + data_rw32 = inl(ulport); + return data_rw32; +} + +void outportb(unsigned long ulport, int data) +{ + outb(data, ulport); +} + +int inportb(unsigned long ulport) +{ + int data_rw8 = 0; + data_rw8 = inb(ulport); + return data_rw8; +} +#endif + +void Write_SIO(unsigned long ulportIdx, unsigned long ulportData, int reg, int val) +{ + outportb(ulportIdx, reg); + outportb(ulportData, val); +} + +unsigned long Read_SIO(unsigned long ulportIdx, unsigned long ulportData, int reg) +{ + outportb(ulportIdx, reg); + return inportb(ulportData); +} + +void Write_SIO32(unsigned long ulportIdx, unsigned long ulportData, int reg, int val) +{ + outportl(ulportIdx, reg); + outportl(ulportData, val); +} + +unsigned long Read_SIO32(unsigned long ulportIdx, unsigned long ulportData, unsigned int reg) +{ + outportl(ulportIdx, reg); + return inportl(ulportData); +} + +//---------------------------------------------------------------------------- +// Define PCI RW +//---------------------------------------------------------------------------- +#define PCH_Wellsburg_PCI_CONFIG_INDEX 0xCF8 +#define PCH_Wellsburg_PCI_CONFIG_DATA 0xCFC +#define PCH_Wellsburg_PCI_MEMORY_ADDR_MASK 0xFFFFFFFE // Bit 0: PCI Spec - Region Type (0: memory, 1: I/O) +#define PCH_Wellsburg_PCI_BDF_32BITS_UNIT 0xFC // PCI read/write uint : 4 bytes. + +#define PCH_WellsburgA_WRITE_FLAG 1 +#define PCH_WellsburgA_READ_FLAG 0 + +//---------------------------------------------------------------------------- +//Platform Controller Unit (PCU) Registers //page.433 (for GPIO) +//---------------------------------------------------------------------------- +#define PCH_Wellsburg_LPC_BUS 0 +#define PCH_Wellsburg_LPC_DEV 0x1F +#define PCH_Wellsburg_LPC_FUN 0 + +//---------------------------------------------------------------------------- +// INTEL PCH SMBus Controller Registers(D31:F3) //Pag.779 SMBus 2.0 #0 Registers +//---------------------------------------------------------------------------- +#define PCH_Wellsburg_SBMUS_CONTROLER_BUS 0 +#define PCH_Wellsburg_SBMUS_CONTROLER_DEV 0x1F //dev 31 = 0x1F +#define PCH_Wellsburg_SBMUS_CONTROLER_FUN 0x04 +#define PCH_Wellsburg_SMBUS_REG_IO_BASE_ADDR 0x20 + +//---------------------------------------------------------------------------- +// INTEL PCH SMBus I/O and Memory Mapped I/O Registers +// Host Status Register (SMB_Mem_HSTS_io)¡XOffset 0h //Page.785 +////---------------------------------------------------------------------------- +#define PCH_Wellsburg_SMB_IOREG_HST_STS 0x00 // Host Status Reg. +#define PCH_Wellsburg_HST_STS_HOST_BUSY 0x01 // R/WC +#define PCH_Wellsburg_HST_STS_INTR 0x02 // R/WC +#define PCH_Wellsburg_HST_STS_DEV_ERR 0x04 // R/WC +#define PCH_Wellsburg_HST_STS_BUS_ERR 0x08 // R/WC +#define PCH_Wellsburg_HST_STS_FAILED 0x10 // R/WC +#define PCH_Wellsburg_HST_STS_SMBALERT_STS 0x20 // R/WC +#define PCH_Wellsburg_HST_STS_INUSE_STS 0x40 // R/WC +#define PCH_Wellsburg_HST_STS_BDS 0x80 // R/WC +#define PCH_Wellsburg_HST_STS_ALL 0xff // R/WC +#define PCH_Wellsburg_HST_STS_ERROR 0x1c // R/WC +#define PCH_Wellsburg_SMB_IOREG_HST_CNT 0x02 // Host Control Reg. +#define PCH_Wellsburg_HST_CNT_INTREN 0x01 // RW +#define PCH_Wellsburg_HST_CNT_KILL 0x02 // RW +#define PCH_Wellsburg_HST_CNT_SMB_CMD 0x1C // RW +#define PCH_Wellsburg_SMB_CMD_BYTE 0x04 //Page 4223 PCU SMBUS I/O Registers +#define PCH_Wellsburg_SMB_CMD_BYTE_DATA 0x08 //Page 4223 PCU SMBUS I/O Registers +#define PCH_Wellsburg_SMB_CMD_WORD_DATA 0x0c //Page 4223 PCU SMBUS I/O Registers +#define PCH_Wellsburg_SMB_CMD_BLOCK 0x14 +#define PCH_Wellsburg_HST_CNT_LAST_BYTE 0x20 // RW +#define PCH_Wellsburg_HST_CNT_START 0x40 // RW +#define PCH_Wellsburg_HST_CNT_PEC_EN 0x80 // RW +#define PCH_Wellsburg_SMB_IOREG_HST_CMD 0x03 // Host Command Reg. +#define PCH_Wellsburg_SMB_IOREG_XMIT_SLVA 0x04 // Transmit Slave Address Reg. // BIT0 : 1 = read, 0 = write +#define PCH_Wellsburg_XMIT_SLVA_RW 0x01 // RW +#define PCH_Wellsburg_SMB_IOREG_HST_D0 0x05 // Host Data 0 +#define PCH_Wellsburg_SMB_IOREG_HST_D1 0x06 // Host Data 1 +#define PCH_Wellsburg_SMB_IOREG_HOST_BLOCK_DB 0x07 // Host Block Data Byte Reg. +#define PCH_Wellsburg_SMB_IOREG_PEC 0x08 // Packet Error Check Reg. +#define PCH_Wellsburg_SMB_IOREG_RCV_SLVA 0x09 // Receive Slave Address Reg. +#define PCH_Wellsburg_SMB_IOREG_SLV_DATA0 0x0a // Receive Slave Data 0 Reg. +#define PCH_Wellsburg_SMB_IOREG_SLV_DATA1 0x0b // Receive Slave Data 1 Reg. +#define PCH_Wellsburg_SMB_IOREG_AUX_STS 0x0c // Auxiliary Status Reg. +#define PCH_Wellsburg_AUX_STS_CRC_ERR 0x01 // R/WC +#define PCH_Wellsburg_AUX_STS_STCO 0x02 // RO +#define PCH_Wellsburg_SMB_IOREG_AUX_CTL 0x0d // Auxiliary Control Reg. +#define PCH_Wellsburg_AUX_CTL_AAC 0x01 // R/W +#define PCH_Wellsburg_AUX_CTL_E32B 0x02 // R/W +#define PCH_Wellsburg_SMB_IOREG_SMLINK_PIN_CTL 0x0e // SMLink Pin Control Reg. +#define PCH_Wellsburg_SMB_IOREG_SMBUS_PIN_CTL 0x0f // SMBus Pin Control Reg. +#define PCH_Wellsburg_SMB_IOREG_SLV_STS 0x10 // Slave Status Reg. +#define PCH_Wellsburg_SMB_IOREG_SLV_CMD 0x11 // Slave Command Reg. +#define PCH_Wellsburg_SMB_IOREG_NOTIFY_DADDR 0x14 // Notify Device Address Reg. +#define PCH_Wellsburg_SMB_IOREG_NOTIFY_DLOW 0x16 // Notify Data Low Reg. +#define PCH_Wellsburg_SMB_IOREG_NOTIFY_DHIGH 0x17 // Notify Data High Reg. + +unsigned int uPCHWellsburgSMBusAddr; + +unsigned char PCH_Wellsburg_Detect_SMBus_Device(unsigned int uSMbusBase, unsigned char ucSlaveID, unsigned char ucReg) +{ + unsigned char ucValue; + + delay(1); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS, 0xFE); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CMD, ucReg); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_XMIT_SLVA, ucSlaveID|0x01); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CNT,0x48); + delay(1); + ucValue = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS); + ucValue = ucValue & PCH_Wellsburg_HST_STS_DEV_ERR; + + //printf("PCH_Wellsburg - Detect_SMBus_Device, STATUS: 0x%x \n", ucValue); + + return ucValue; +} + +unsigned char PCH_Wellsbur_Read_SMBus(unsigned int uSMbusBase, unsigned char ucSlaveID, unsigned char ucReg) +{ + unsigned char ucValue = 0xff; + unsigned char ucStatus; + int i, j; + + for(i = 0; i < 100; i++) + { + delay(1); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS, 0xFE); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CMD, ucReg); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_XMIT_SLVA, ucSlaveID|0x01); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CNT,0x48); + + for(j = 0; j < 100; j++) + { + delay(1); + ucStatus = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS); + if((ucStatus & PCH_Wellsburg_HST_STS_HOST_BUSY) != PCH_Wellsburg_HST_STS_HOST_BUSY) + break; + } + + ucValue = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_D0); + + if((ucStatus & (PCH_Wellsburg_HST_STS_HOST_BUSY | PCH_Wellsburg_HST_STS_DEV_ERR)) == 0x00) + break; + + } + + //printf("read - i: %x, j : 0x%x, slave : %x, reg : 0x%x, value: 0x%x, status:%x \n", i, j, ucSlaveID, ucReg, ucValue, ucStatus); + + return ucValue; +} + +void PCH_Wellsbur_Write_SMBus(unsigned int uSMbusBase, unsigned char ucSlaveID, unsigned char ucReg, unsigned char ucValue) +{ + unsigned char ucData = 0xff; + + unsigned char ucStatus; + int i, j; + + for(i = 0; i < 100; i++) + { + delay(1); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS, 0xFE); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CMD, ucReg); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_XMIT_SLVA, (ucSlaveID & (~0x1))); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_D0, ucValue); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CNT, 0x48); + + for(j = 0; j < 100; j++) + { + delay(1); + ucStatus = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS); + if((ucStatus & PCH_Wellsburg_HST_STS_HOST_BUSY) != PCH_Wellsburg_HST_STS_HOST_BUSY) + break; + } + + if((ucStatus & (PCH_Wellsburg_HST_STS_HOST_BUSY | PCH_Wellsburg_HST_STS_DEV_ERR)) == 0x00) + break; + } + + //printf("write - i: %x, j : 0x%x, slave : %x, reg : 0x%x, value: 0x%x, status:%x \n", i, j, ucSlaveID, ucReg, ucValue, ucStatus); +} + +// 2017/07/10 PSU - Add SMBUS short mode. +unsigned short PCH_Wellsbur_Read_SMBus_Word(unsigned int uSMbusBase, unsigned char ucSlaveID, unsigned char ucReg) +{ + unsigned char ucValue0, ucValue1; + unsigned char ucStatus; + unsigned short usData; + int i, j; + + for(i = 0; i < 100; i++) + { + delay(1); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS, 0xFE); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CMD, ucReg); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_XMIT_SLVA, ucSlaveID|0x01); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CNT,0x4C); + + for(j = 0; j < 100; j++) + { + delay(1); + ucStatus = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS); + if((ucStatus & PCH_Wellsburg_HST_STS_HOST_BUSY) != PCH_Wellsburg_HST_STS_HOST_BUSY) + break; + } + + ucValue0 = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_D0); + ucValue1 = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_D1); + usData = (ucValue1 << 8) + ucValue0; + + if((ucStatus & (PCH_Wellsburg_HST_STS_HOST_BUSY | PCH_Wellsburg_HST_STS_DEV_ERR)) == 0x00) + break; + + } + + //printf("read - i: %x, j : 0x%x, slave : %x, reg : 0x%x, value: 0x%x, status:%x \n", i, j, ucSlaveID, ucReg, ucValue, ucStatus); + + return usData; +} + + +// 2017/07/10 PSU - Add SMBUS short mode. +void PCH_Wellsbur_Write_SMBus_Word(unsigned int uSMbusBase, unsigned char ucSlaveID, unsigned char ucReg, unsigned short usValue) +{ + unsigned char ucData0, ucData1; + unsigned char ucStatus; + int i, j; + + ucData0 = (unsigned char)(usValue & 0xff); + ucData1 = (unsigned char)((usValue & 0xff00) >> 8); + + for(i = 0; i < 100; i++) + { + delay(1); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS, 0xFE); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CMD, ucReg); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_XMIT_SLVA, (ucSlaveID & (~0x1))); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_D0, ucData0); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_D1, ucData1); + outportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_CNT, 0x4C); + + for(j = 0; j < 100; j++) + { + delay(1); + ucStatus = inportb(uSMbusBase + PCH_Wellsburg_SMB_IOREG_HST_STS); + if((ucStatus & PCH_Wellsburg_HST_STS_HOST_BUSY) != PCH_Wellsburg_HST_STS_HOST_BUSY) + break; + } + + if((ucStatus & (PCH_Wellsburg_HST_STS_HOST_BUSY | PCH_Wellsburg_HST_STS_DEV_ERR)) == 0x00) + break; + } + + //printf("write - i: %x, j : 0x%x, slave : %x, reg : 0x%x, value: 0x%x, status:%x \n", i, j, ucSlaveID, ucReg, ucValue, ucStatus); +} + +unsigned int PCH_Wellsburg_get_PCI_base_addr(unsigned char ucBusNum, unsigned char ucDevNum, unsigned char ucFuncNum, unsigned char ucRegNum) +{ + unsigned int BusDevFunc; + unsigned int temp, addr; + + BusDevFunc =(ucBusNum << 8 ) + ( ucDevNum << 3) + (ucFuncNum) ; + temp = (unsigned int)(0x80000000 | (BusDevFunc<<8) | (ucRegNum & PCH_Wellsburg_PCI_BDF_32BITS_UNIT)) ; + addr = Read_SIO32( PCH_Wellsburg_PCI_CONFIG_INDEX, PCH_Wellsburg_PCI_CONFIG_DATA, temp ); + addr = addr & PCH_Wellsburg_PCI_MEMORY_ADDR_MASK; + + return addr; +} + +void PCH_Wellsburg_get_SMBus_base_addr() +{ + uPCHWellsburgSMBusAddr = PCH_Wellsburg_get_PCI_base_addr(PCH_Wellsburg_SBMUS_CONTROLER_BUS, PCH_Wellsburg_SBMUS_CONTROLER_DEV, PCH_Wellsburg_SBMUS_CONTROLER_FUN, PCH_Wellsburg_SMBUS_REG_IO_BASE_ADDR); +} + +// ============================================================================ +// "FPGA Initial and Uninitial Function. +// Parameters: +// Number : 4 +// argv[0] : Slave Id +// argv[1] : interface +// argv[2] : register of port index +// argv[3] : register of port data +// ============================================================================ +int PCH_Wellsburg_init(int argc, unsigned long argv[]) +{ + unsigned long ulAddrHI, ulAddrLO; + int i, rc; + +#ifdef __linux + iopl(3); +#endif + + //ESDK_printf("argc : 0x%x, 0:0x%x, 1:0x%x, 2: 0x%x, 3:0x%x \r\n ", 4, argv[0], argv[1], argv[2], argv[3]); + + PCH_Wellsburg_get_SMBus_base_addr(); +// PCH_Wellsburg_set_GPIO_control(); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 4 +// argv[0] : Slave Id +// argv[1] : interface +// argv[2] : register of port index +// argv[3] : register of port data +// ============================================================================ +int PCH_Wellsburg_uninit(int argc, unsigned long argv[]) +{ + + if(argv[4] == 0x01) + { + #ifdef __linux + iopl(0); + #endif + } + + return 0; +} + +#define NCT6791D_START_CHAR 0x87 +#define NCT6791D_END_CHAR 0xAA +#define NCT6791D_WRITE_FLAG 1 +#define NCT6791D_READ_FLAG 0 +#define NCT6791D_LND_REG 0x07 +// GPIO +#define NCT6791D_GPIO_GROUP_NUMBER 9 +#define NCT6791D_GPIO_EN_REG 0x30 + +// HardWare Monitor +#define NCT6791D_HWMonitor_LND 0x0B +#define NCT6791D_HWMonitor_EN_REG 0x30 +#define NCT6791D_HWMonitor_EN 0x01 +#define NCT6791D_HWMonitor_ADDR_HI_REG 0x60 +#define NCT6791D_HWMonitor_ADDR_LO_REG 0x61 +#define NCT6791D_HWMonitor_BANK_SEL_REG 0x4E +#define NCT6791D_HWMonitor_DATA_BANK 4 +#define NCT6791D_HWMonitor_PECI_BANK 7 +#define NCT6791D_GPIO_PUSH_PULL_OD_LND 0xF +//----------------------PIO0X, GPIO1X, GPIO2X, GPIO3X, GPIO4X, GPIO5X, GPIO6X, GPIO7X, GPIO8X +unsigned char NCT6791D_GPIO_LND[] = {8, 8, 9, 9, 9, 9, 7, 7, 7}; +unsigned char NCT6791D_GPIO_EN_BIT[] = {1, 7, 0, 1, 2, 3, 0, 1, 2}; +unsigned char NCT6791D_GPIO_OUTPUT_EN_REG[] = {0xe0, 0xf0, 0xe0, 0xe4, 0xf0, 0xf4, 0xf4, 0xe0, 0xe4}; //Assign bit to 0. +unsigned char NCT6791D_GPIO_DATA_REG[] = {0xe1, 0xf1, 0xe1, 0xe5, 0xf1, 0xf5, 0xf5, 0xe1, 0xe5}; +unsigned char NCT6791D_GPIO_MULTIFUNC_REG[] = {0xe4, 0xf4, 0xe9, 0xeA, 0xee, 0xeb, 0xf8, 0xec, 0xed}; +unsigned char NCT6791D_GPIO_MULTIFUNC_VALUE[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; +unsigned char NCT6791D_GPIO_PUSH_PULL_OD_REG[] = {0xE9, 0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7}; +unsigned char NCT6791D_GPIO_PUSH_PULL_OD_VALUE[] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; + + +unsigned char NCT6791D_ucLDN = 0xff; // Save Logic Device Number Register (LDN) +unsigned long NCT6791D_HWMonitor_addr; + +void NCT6791D_Enter_SIO(unsigned long ulportIdx) +{ + outportb(ulportIdx, NCT6791D_START_CHAR); + delay(1); + outportb(ulportIdx, NCT6791D_START_CHAR); +} + +void NCT6791D_Exit_SIO(unsigned long ulportIdx) +{ + outportb(ulportIdx, NCT6791D_END_CHAR); +} + +// ============================================================================ +// "FPGA Initial and Uninitial Function. +// Parameters: +// Number : 4 +// argv[0] : Slave Id +// argv[1] : interface +// argv[2] : register of port index +// argv[3] : register of port data +// ============================================================================ +int NCT6791D_init(int argc, unsigned long argv[]) +{ + unsigned long ulAddrHI, ulAddrLO; + unsigned char ucData; + int i, rc; + +#ifdef __linux + iopl(3); +#endif + + //ESDK_printf("argc : 0x%x, 0:0x%x, 1:0x%x, 2: 0x%x, 3:0x%x \r\n ", 4, argv[0], argv[1], argv[2], argv[3]); + + switch(argv[1]) + { + case 'P': + + NCT6791D_Enter_SIO(argv[2]); + + // Get Hardware Monitor mapping address + Write_SIO(argv[2], argv[3], NCT6791D_LND_REG, NCT6791D_HWMonitor_LND); // Logic Device Number Register (LDN) : 4 + Write_SIO(argv[2], argv[3], NCT6791D_HWMonitor_EN_REG, NCT6791D_HWMonitor_EN); + ulAddrHI = Read_SIO(argv[2], argv[3], NCT6791D_HWMonitor_ADDR_HI_REG); + ulAddrLO = Read_SIO(argv[2], argv[3], NCT6791D_HWMonitor_ADDR_LO_REG); + NCT6791D_HWMonitor_addr = ulAddrHI * 0x100 + ulAddrLO; + // Set HWMonitor data bank : 4 + Write_SIO(NCT6791D_HWMonitor_addr + 5, NCT6791D_HWMonitor_addr + 6, NCT6791D_HWMonitor_BANK_SEL_REG, NCT6791D_HWMonitor_DATA_BANK); + + break; + + default: + //break; + return ERR_DEVICE_TABLE; + } + + //ESDK_printf("NCT6791D_HWMonitor_addr : 0x%x \r\n ", NCT6791D_HWMonitor_addr); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 4 +// argv[0] : Slave Id +// argv[1] : interface +// argv[2] : register of port index +// argv[3] : register of port data +// ============================================================================ +int NCT6791D_uninit(int argc, unsigned long argv[]) +{ + //printf("NCT6791D_uninit - argv1 : %c, argv2: 0x%x \n", argv[1], argv[2]); + + switch(argv[1]) + { + case 'P': + NCT6791D_Exit_SIO(argv[2]); + break; + + default: + //break; + return ERR_DEVICE_TABLE; + } + + if(argv[4] == 0x01) + { + #ifdef __linux + iopl(0); + #endif + } + + return 0; +} + +// ============================================================================ +// "General "GPIO" Functions. +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_get_configure(unsigned char outputFlag, unsigned long ulReg, unsigned long *ucValue, int argc, unsigned long argv[]) +{ + unsigned char ucInterface; + unsigned char ucSlaveID; + unsigned long ulportIdx; + unsigned long ulportData; + + ucInterface = argv[2]; + ucSlaveID = argv[3]; + ulportIdx = argv[4]; + ulportData = argv[5]; + + switch(ucInterface) + { + case 'P': + if(outputFlag) + Write_SIO(ulportIdx, ulportData, ulReg, *ucValue); + else + *ucValue = Read_SIO(ulportIdx, ulportData, ulReg); + break; + + default: + //break; + return ERR_DEVICE_TABLE; + } + + //ESDK_printf("GPIO - *ucValue : 0x%x \r\n", *ucValue); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_switch_default_function(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulIdx; + int i; + + // GPIO0X + if((argv[0] / 0x10) == 0x0) + { + ulReg = 0x1c; + if(argv[0] < 0x03) + { + // CR1C[0]=1, CR1C[1]=1, CR1C[2]=1 + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulIdx = argv[0]%0x10; + ulData |= (1 << ulIdx); + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x03) + { + //CR1C[4:3]=00 + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xe7; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] < 0x07) + { + // CR1C[5]=1, CR1C[6]=1, CR1C[7]=1 + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulIdx = argv[0]%0x10; + ulIdx++; + ulData |= (1 << ulIdx); + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + } + // GPIO2X + else if((argv[0] / 0x10) == 0x2) + { + if((argv[0] == 0x20)||(argv[0] == 0x21)) + { + // CR2A[0]=1 + ulReg = 0x2a; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData |= 0x1; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if((argv[0] == 0x22)||(argv[0] == 0x23)) + { + // CR2A[1]=1 + ulReg = 0x2a; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData |= 0x2; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x24) + { + // CR1B[4]=0, CR27[3]=0 + ulReg = 0x1b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xef; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + ulReg = 0x27; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xf7; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x26) + { + // CR2C[0]=0 + ulReg = 0x2c; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xfe; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + } + // GPIO3X + else if((argv[0] / 0x10) == 0x3) + { + if(argv[0] == 0x30) + { + // CR1A[7:6]=01 + ulReg = 0x1a; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0x3f; + ulData |= 0x40; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x33) + { + // CR2C[6:5]=01 + ulReg = 0x2c; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0x9f; + ulData |= 0x20; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if((argv[0] == 0x34)||(argv[0] == 0x35)||(argv[0] == 0x36)) + { + // CR27[4]=0 + ulReg = 0x27; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xef; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + } + // GPIO4X + else if((argv[0] / 0x10) == 0x4) + { + if(argv[0] == 0x40) + { + // CR1B[3]=1 + ulReg = 0x1b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData |= 0x08; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x41) + { + // CR1A[3:2]=10, CR27[4]=0 + ulReg = 0x1a; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xf3; + ulData |= 0x80; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + ulReg = 0x27; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xef; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x42) + { + // CR1B[2:1]=11, CR27[4]=0 + ulReg = 0x1b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xf9; + ulData |= 0x60; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + ulReg = 0x27; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xef; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x43) + { + // CR27[4]=0 + ulReg = 0x27; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xef; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if((argv[0] == 0x44)||(argv[0] == 0x45)) + { + // CR1B[6]=0, CR27[4]=0 + ulReg = 0x1b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xbf; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + ulReg = 0x27; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xef; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x47) + { + // CR1B[7]=1 + ulReg = 0x1b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData |= 0x80; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + } + // GPIO5X + else if((argv[0] / 0x10) == 0x5) + { + if(argv[0] == 0x50) + { + // LDB CRE6[2]=0 + ulReg = 0xe6; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xfb; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x51) + { + // CR2D[1]=0 + ulReg = 0x2d; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xfd; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x52) + { + // LDB CRE6[1]=0 + ulReg = 0xe6; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xfd; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x53) + { + // CR2D[0]=0 + ulReg = 0x2d; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xfe; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x54) + { + // CR1D[3]=0 + ulReg = 0x1d; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xf7; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x55) + { + // LDB CRE6[3]=0 + ulReg = 0xe6; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xf7; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if((argv[0] == 0x56)||(argv[0] == 0x57)) + { + // Strapping by AMDPWR_EN or CR2F[5] + // CR2F[5]=0 + ulReg = 0x2f; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xdf; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + } + // GPIO6X + else if((argv[0] / 0x10) == 0x6) + { + // CR27[4]=0 + ulReg = 0x27; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xef; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + // GPIO7X + else if((argv[0] / 0x10) == 0x7) + { + if(argv[0] < 0x74) + { + // Strapping by TEST2_MODE_EN or CR2F[2] + // CR2F[2]=0 + ulReg = 0x2f; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData &= 0xfb; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x74) + { + // CR2B[5]=1 + ulReg = 0x2b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData |= 0x20; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x75) + { + // CR2B[6]=1 + ulReg = 0x2b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData |= 0x40; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + else if(argv[0] == 0x76) + { + // CR2B[7]=1 + ulReg = 0x2b; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulData |= 0x80; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + } + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_set_push_pull_mode_function(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulIdx, ulTempData; + int i; + + // Set Logic device F + ulReg = NCT6791D_LND_REG; + ulData = NCT6791D_GPIO_PUSH_PULL_OD_LND; + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + + // Set push_pull mode + ulIdx = argv[0]%0x10; + ulReg = NCT6791D_GPIO_PUSH_PULL_OD_REG[argv[0]/0x10]; + NCT6791D_GPIO_get_configure( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + + ulData &= ~(1 << ulIdx); + ulTempData = NCT6791D_GPIO_PUSH_PULL_OD_VALUE[ulIdx] & (1 << ulIdx); + ulData |= ulTempData; + + NCT6791D_GPIO_get_configure( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + +} + +// ============================================================================ +// "General "GPIO" Functions. +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : setting value +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_get_data(unsigned char outputFlag, unsigned long ulReg, unsigned long *ucValue, int argc, unsigned long argv[]) +{ + unsigned char ucInterface; + unsigned char ucSlaveID; + unsigned long ulportIdx; + unsigned long ulportData; + unsigned char ucData; + int index; + + ucInterface = argv[2]; + ucSlaveID = argv[3]; + ulportIdx = argv[4]; + ulportData = argv[5]; + + index = argv[0] / 0x10; + //if(NCT6791D_ucLDN != NCT6791D_GPIO_LND[index]) + { + Write_SIO(ulportIdx, ulportData, NCT6791D_LND_REG, NCT6791D_GPIO_LND[index]); + NCT6791D_ucLDN = NCT6791D_GPIO_LND[index]; + } + + //ESDK_printf("GPIO - NCT6791D_ucLDN: 0x%x, outputFlag : 0x%x, ulReg : 0x%x, *ucValue: 0x%x, ulportIdx :0x%x,ulportData : 0x%x \r\n", NCT6791D_ucLDN, outputFlag, ulReg, *ucValue, ulportIdx, ulportData); + + switch(ucInterface) + { + case 'P': + if(outputFlag) + Write_SIO(ulportIdx, ulportData, ulReg, *ucValue); + else + *ucValue = Read_SIO(ulportIdx, ulportData, ulReg); + break; + + default: + //break; + return ERR_DEVICE_TABLE; + } + + //ESDK_printf("GPIO - *ucValue : 0x%x \r\n", *ucValue); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : Enable/Disable(0:Disable, 1:Enable) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_set_enable(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData, ulTempData, ulEnable; + unsigned long ulIdx; + + ulEnable = argv[1]; + ulIdx = argv[0] / 0x10; + ulReg = NCT6791D_GPIO_EN_REG; + + NCT6791D_GPIO_get_data( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + ulTempData = (1 << NCT6791D_GPIO_EN_BIT[ulIdx]); + ulData &= (~ulTempData); + if(ulEnable > 0) + ulData |= ulTempData; + + NCT6791D_GPIO_get_data( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : IO setting(0:Input, 1:Output) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_set_IO(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulTempData; + int i; + + ulReg = NCT6791D_GPIO_OUTPUT_EN_REG[argv[0] / 0x10]; + ulTempData = argv[1]; + + NCT6791D_GPIO_get_data( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + ulData = ulData & (~(1 << i)); // 0: Output + if(ulTempData == 0) + ulData |= (1 << i); // 1: Input + + NCT6791D_GPIO_get_data( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : IO setting(0:Input, 1:Output) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_get_IO(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + int i; + + ulReg = NCT6791D_GPIO_OUTPUT_EN_REG[argv[0] / 0x10]; + +// ESDK_printf("NCT6791D_GPIO_get_IO - argv[0] : 0x%x, index: %x, ulReg:0x%x \r\n", argv[0], argv[0] / 0x10, ulReg); + + NCT6791D_GPIO_get_data( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + if((ulData & (1 << i)) > 0) + argv[1] = 0; + else + argv[1] = 1; + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : IO setting(0:Input, 1:Output) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_set_multifunction(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulTempData, ulIO; + int i; + + ulIO = argv[1]; + + //Switch default function to GPIO + NCT6791D_GPIO_switch_default_function(argc, argv); + + //Enable GPIO + argv[1] = 1; + NCT6791D_GPIO_set_enable(argc, argv); + + // Set multifunctions. + ulReg = NCT6791D_GPIO_MULTIFUNC_REG[argv[0] / 0x10]; + ulTempData = NCT6791D_GPIO_MULTIFUNC_VALUE[argv[0] / 0x10]; + NCT6791D_GPIO_get_data( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + ulData = ulData & (~(1 << i)); + ulTempData = ulTempData & (1 << i); + ulData |= ulTempData; + NCT6791D_GPIO_get_data( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + + // Set GPIO Push-pull or Open-drain selection (set Push-pull mode) + NCT6791D_GPIO_set_push_pull_mode_function(argc, argv); + + //Reset GPIO input/output + argv[1] = ulIO; + NCT6791D_GPIO_set_IO(argc, argv); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : data +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_set_output_value(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulTempData; + int i; + + ulReg = NCT6791D_GPIO_DATA_REG[argv[0] / 0x10]; + ulTempData = argv[1]; + + //ESDK_printf("NCT6791D_GPIO_set_value - argv[0] : 0x%x, index: %x, ulReg:0x%x \r\n", argv[0], argv[0] / 0x10, ulReg); + + NCT6791D_GPIO_get_data( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + ulData = (ulData & (~(1 << i))) | (ulTempData << i); + NCT6791D_GPIO_get_data( NCT6791D_WRITE_FLAG, ulReg, &ulData, argc, argv); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : data +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_get_output_value(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + int i; + + ulReg = NCT6791D_GPIO_DATA_REG[argv[0] / 0x10]; + + NCT6791D_GPIO_get_data( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + argv[1] = (ulData & (1 << i)) >> i; + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : data +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT6791D_GPIO_get_input_value(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + int i; + + ulReg = NCT6791D_GPIO_DATA_REG[argv[0] / 0x10]; + + NCT6791D_GPIO_get_data( NCT6791D_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + argv[1] = (ulData & (1 << i)) >> i; + + return 0; +} +unsigned char NCT5605Y_SMBUS_Detect(int argc, unsigned long argv[]) +{ + + return PCH_Wellsburg_Detect_SMBus_Device( uPCHWellsburgSMBusAddr, (unsigned char)argv[0], (unsigned char)argv[1]); +} + +unsigned char NCT5605Y_SMBUS_Read(int argc, unsigned long argv[]) +{ + + return PCH_Wellsbur_Read_SMBus( uPCHWellsburgSMBusAddr, (unsigned char)argv[0], (unsigned char)argv[1]); +} + +void NCT5605Y_SMBUS_Write(int argc, unsigned long argv[]) +{ + + PCH_Wellsbur_Write_SMBus( uPCHWellsburgSMBusAddr, (unsigned char)argv[0], (unsigned char)argv[1], (unsigned char)argv[2]); +} + +#define NCT5605Y_READ_FLAG 0 +#define NCT5605Y_WRITE_FLAG 1 +// Slave ID +unsigned char NCT5605Y_SLAVE_ID[] = {0x30,0x32,0x34,0x36,0x38,0x3A,0x3C,0x3E}; +//----------------------XXXX, GPIO1X, GPIO2X +unsigned char NCT5605Y_GPIO_OUTPUT_EN_REG[] = {0xff, 0x03, 0x13}; //Assign bit yo 0. +unsigned char NCT5605Y_GPIO_INPUT_DATA_REG[] = {0xff, 0x00, 0x10}; +unsigned char NCT5605Y_GPIO_OUTPUT_DATA_REG[] = {0xff, 0x01, 0x11}; + +unsigned long NCT5605Y_SMBUS_addr; + +// ============================================================================ +// "FPGA Initial and Uninitial Function. +// Parameters: +// Number : 4 +// argv[0] : Slave Id +// argv[1] : interface +// argv[2] : register of port index / base address +// argv[3] : register of port data +// ============================================================================ +int NCT5605Y_init(int argc, unsigned long argv[]) +{ + unsigned char ucDeviceStatus; + unsigned long ulSMBusarg[3]; + int i, rc; + +#ifdef __linux + iopl(3); +#endif + + //ESDK_printf("argc : 0x%x, 0:0x%x, 1:0x%x, 2: 0x%x, 3:0x%x \r\n ", 4, argv[0], argv[1], argv[2], argv[3]); + + switch(argv[1]) + { + case 'S': + + NCT5605Y_SMBUS_addr = 0x00; + if(argv[0] != 0x00) + { + ulSMBusarg[0] = argv[0]; + ulSMBusarg[1] = 0x00; + ucDeviceStatus = NCT5605Y_SMBUS_Detect(2, ulSMBusarg); + + //ESDK_printf("smbus_slave_status : 0x%x \n", ucDeviceStatus); + + // PCH_Wellsburg_HST_STS_DEV_ERR bit is zero. + if(ucDeviceStatus == 0x00) + { + NCT5605Y_SMBUS_addr = argv[0]; + }else{ + return ERR_MCU_NO_DEVICE; + } + + }else + { + for(i = 0; i < sizeof(NCT5605Y_SLAVE_ID); i++) + { + ulSMBusarg[0] = NCT5605Y_SLAVE_ID[i]; + ulSMBusarg[1] = 0x00; + NCT5605Y_SMBUS_Detect(2, ulSMBusarg); + ucDeviceStatus = ulSMBusarg[2]; + + //ESDK_printf("smbus_slave_status : 0x%x \n", ucDeviceStatus); + + // PCH_Wellsburg_HST_STS_DEV_ERR bit is zero. + if(ucDeviceStatus == 0x00) + { + NCT5605Y_SMBUS_addr = NCT5605Y_SLAVE_ID[i]; + break; + } + } + } + + //ESDK_printf("NCT5605Y_SMBUS_addr : 0x%x \n", NCT5605Y_SMBUS_addr); + + break; + + default: + //break; + return ERR_DEVICE_TABLE; + } + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 4 +// argv[0] : Slave Id +// argv[1] : interface +// argv[2] : register of port index +// argv[3] : register of port data +// ============================================================================ +int NCT5605Y_uninit(int argc, unsigned long argv[]) +{ + if(argv[4] == 0x01) + { + #ifdef __linux + iopl(0); + #endif + } + + return 0; +} +// ============================================================================ +// "General "GPIO" Functions. +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : IO setting(1:Input, 0:Output) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT5605Y_GPIO_get_data(unsigned char outputFlag, unsigned long ulReg, unsigned long *ucValue, int argc, unsigned long argv[]) +{ + unsigned char ucInterface; + unsigned char ucSlaveID; + unsigned long ulportIdx; + unsigned long ulportData; + unsigned long ulSMBusarg[16]; + + ucInterface = argv[2]; + ucSlaveID = argv[3]; + ulportIdx = argv[4]; + ulportData = argv[5]; + + //ESDK_printf("GPIO - outputFlag : 0x%x, ulReg : 0x%x, *ucValue: 0x%x, ulportIdx :0x%x,ulportData : 0x%x \r\n", outputFlag, ulReg, *ucValue, ulportIdx, ulportData); + //ESDK_printf("SMBUS - interface : 0x%x, ucSlave : 0x%x \r\n", ucInterface, ucSlaveID); + + + switch(ucInterface) + { + case 'S': + if(ucSlaveID == 0x00) + { + *ucValue = 0; + return ERR_GPIO_SMBUS_NO_DEVICE; + } + + ulSMBusarg[0] = ucSlaveID; + ulSMBusarg[1] = ulReg; + ulSMBusarg[2] = *ucValue; + + if(outputFlag) + NCT5605Y_SMBUS_Write(3, ulSMBusarg); + else + *ucValue = NCT5605Y_SMBUS_Read(3, ulSMBusarg); + + break; + + default: + //break; + return ERR_BOARD_TABLE; + } + + //ESDK_printf("GPIO - *ucValue : 0x%x \r\n", *ucValue); + + return 0; +} + +int NCT5605Y_GPIO_Check(unsigned long ulReg) +{ + unsigned char ucIdx; + unsigned char ucReg = (unsigned char)ulReg; + + ucIdx = ucReg / 0x10; + if((ucReg == 0) || (ucIdx > 2)) + { + return ERR_GPIO_REGISTER; + } + + if((ucReg == 2) && ((ucReg % 0x10) > 5)) + { + return ERR_GPIO_REGISTER; + } + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : IO setting(1:Input, 0:Output) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT5605Y_GPIO_set_IO(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulTempData; + int i, rc; + + rc = NCT5605Y_GPIO_Check(argv[0]); + if(rc < 0) + return rc; + + ulReg = NCT5605Y_GPIO_OUTPUT_EN_REG[argv[0] / 0x10]; + ulTempData = argv[1]; + if(argv[1] == 0) + ulTempData = 0x1; + else + ulTempData = 0x0; + + NCT5605Y_GPIO_get_data( NCT5605Y_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + ulData = (ulData & (~(1 << i))) | (ulTempData << i); + NCT5605Y_GPIO_get_data( NCT5605Y_WRITE_FLAG, ulReg, &ulData, argc, argv); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : IO setting(1:Input, 0:Output) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT5605Y_GPIO_get_IO(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + int i, rc; + + rc = NCT5605Y_GPIO_Check(argv[0]); + if(rc < 0) + return rc; + + ulReg = NCT5605Y_GPIO_OUTPUT_EN_REG[argv[0] / 0x10]; + +// ESDK_printf("NCT5605Y_GPIO_get_IO - argv[0] : 0x%x, index: %x, ulReg:0x%x \r\n", argv[0], argv[0] / 0x10, ulReg); + + NCT5605Y_GPIO_get_data( NCT5605Y_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + argv[1] = (ulData & (1 << i)) >> i; + + if(argv[1] == 0) + argv[1] = 0x01; + else + argv[1] = 0x00; + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : IO setting(0:Input, 1:Output) +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT5605Y_GPIO_set_multifunction(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulIO; + int i; + + ulIO = argv[1]; + + // Close LED function + if((argv[0] / 0x10) == 1) + { + if(argv[0] < 0x14) + { + ulReg = 0x08; + NCT5605Y_GPIO_get_data( NCT5605Y_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + ulData &= (~(3 << (i*2))); + NCT5605Y_GPIO_get_data( NCT5605Y_WRITE_FLAG, ulReg, &ulData, argc, argv); + } + } + + //Reset GPIO input/output + argv[1] = ulIO; + NCT5605Y_GPIO_set_IO(argc, argv); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : data +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT5605Y_GPIO_set_output_value(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + unsigned long ulTempData; + int i, rc; + + rc = NCT5605Y_GPIO_Check(argv[0]); + if(rc < 0) + return rc; + + ulReg = NCT5605Y_GPIO_OUTPUT_DATA_REG[argv[0] / 0x10]; + ulTempData = argv[1]; + + //ESDK_printf("NCT5605Y_GPIO_set_value - argv[0] : 0x%x, data: %x, ulReg:0x%x \r\n", argv[0], ulTempData, ulReg); + + NCT5605Y_GPIO_get_data( NCT5605Y_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + ulData = (ulData & (~(1 << i))) | (ulTempData << i); + NCT5605Y_GPIO_get_data( NCT5605Y_WRITE_FLAG, ulReg, &ulData, argc, argv); + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : data +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT5605Y_GPIO_get_output_value(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + int i, rc; + + rc = NCT5605Y_GPIO_Check(argv[0]); + if(rc < 0) + return rc; + + ulReg = NCT5605Y_GPIO_OUTPUT_DATA_REG[argv[0] / 0x10]; + + NCT5605Y_GPIO_get_data( NCT5605Y_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + argv[1] = (ulData & (1 << i)) >> i; + + return 0; +} + +// ============================================================================ +// Parameters: +// Number : 6 +// argv[0] : GPIOXX +// argv[1] : data +// argv[2] : interface +// argv[3] : Slave Id +// argv[4] : register of port index +// argv[5] : register of port data +// ============================================================================ +int NCT5605Y_GPIO_get_input_value(int argc, unsigned long argv[]) +{ + unsigned long ulReg; + unsigned long ulData; + int i, rc; + + rc = NCT5605Y_GPIO_Check(argv[0]); + if(rc < 0) + return rc; + + ulReg = NCT5605Y_GPIO_INPUT_DATA_REG[argv[0] / 0x10]; + + NCT5605Y_GPIO_get_data( NCT5605Y_READ_FLAG, ulReg, &ulData, argc, argv); + i = argv[0] % 0x10; + argv[1] = (ulData & (1 << i)) >> i; + + return 0; +} + + +void help() +{ + printf("============================================\n"); + printf(" GPIO Test program \n"); + printf("============================================\n"); + printf("gpio -r Show All Data \n"); + printf("gpio -54h set GPO54 high \n"); + printf("gpio -54l set GPO54 low \n"); + printf("gpio -55h set GPO55 high \n"); + printf("gpio -55l set GPO55 low \n"); + printf("gpio -56h set GPO56 high \n"); + printf("gpio -56l set GPO56 low \n"); + printf("gpio -57h set GPO57 high \n"); + printf("gpio -57l set GPO57 low \n"); + printf("============================================\n"); +} + +int main(int argc, char* main_argv[]) +{ + unsigned long argv[32]; + int i = 0; + + if (argc!=2){ + help(); + return -1; + } + + argv[0] = 0x00; + argv[1] = 0x00; + argv[2] = 0x00; + argv[3] = 0x00; + argv[4] = 0x00; + PCH_Wellsburg_init(5, argv); + + argv[0] = 0x0; + argv[1] = 'P'; + argv[2] = 0x2e; + argv[3] = 0x2f; + argv[4] = 0x00; + NCT6791D_init(4, argv); + + // Set GPIO configure data. + argv[1] = 0x1; + argv[0] = 0x54; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_multifunction(6, argv); + argv[1] = 0x1; + argv[0] = 0x55; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_multifunction(6, argv); + argv[1] = 0x1; + argv[0] = 0x56; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_multifunction(6, argv); + argv[1] = 0x1; + argv[0] = 0x57; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_multifunction(6, argv); + + // Get GPIO value. + if(strcmp(main_argv[1], "-r") == 0) + { + // Read all GPIO value. + argv[0] = 0x54; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_get_output_value(6, argv); + printf("GPO54 : %lu\n", argv[1]); + argv[0] = 0x55; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_get_output_value(6, argv); + printf("GPO55 : %lu\n", argv[1]); + + argv[0] = 0x56; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_get_output_value(6, argv); + printf("GPO56 : %lu\n", argv[1]); + + argv[0] = 0x57; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_get_output_value(6, argv); + printf("GPO57 : %lu\n", argv[1]); + + } + + // Set GPIO ouput value. + if(strcmp(main_argv[1], "-54h") == 0) + { + argv[1] = 0x1; + argv[0] = 0x54; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO54 to high.\n"); + } + if(strcmp(main_argv[1], "-54l") == 0) + { + argv[1] = 0x0; + argv[0] = 0x54; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO54 to low.\n"); + } + if(strcmp(main_argv[1], "-55h") == 0) + { + argv[1] = 0x1; + argv[0] = 0x55; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO55 to high.\n"); + } + if(strcmp(main_argv[1], "-55l") == 0) + { + argv[1] = 0x0; + argv[0] = 0x55; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO55 to low.\n"); + } + if(strcmp(main_argv[1], "-56h") == 0) + { + argv[1] = 0x1; + argv[0] = 0x56; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO56 to high.\n"); + } + if(strcmp(main_argv[1], "-56l") == 0) + { + argv[1] = 0x0; + argv[0] = 0x56; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO56 to low.\n"); + } + if(strcmp(main_argv[1], "-57h") == 0) + { + argv[1] = 0x1; + argv[0] = 0x57; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO57 to high.\n"); + } + if(strcmp(main_argv[1], "-57l") == 0) + { + argv[1] = 0x0; + argv[0] = 0x57; + argv[2] = 'P'; + argv[3] = 0x0; + argv[4] = 0x2e; + argv[5] = 0x2f; + NCT6791D_GPIO_set_output_value(6, argv); + printf("Set GPO57 to low.\n"); + } + + // Uninitial GPIO chip. + argv[0] = 0x0; + argv[1] = 'P'; + argv[2] = 0x2e; + argv[3] = 0x2f; + argv[4] = 0x00; + NCT6791D_uninit(5, argv); + + argv[0] = 0x00; + argv[1] = 0x00; + argv[2] = 0x00; + argv[3] = 0x00; + argv[4] = 0x00; + PCH_Wellsburg_uninit(5, argv); +#ifdef __linux + iopl(0); +#endif + return 0; +} Index: /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/makefile =================================================================== --- /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/makefile (revision 0) +++ /branches/rel_apv_10_7/usr/click/bin/aewin_cb1920/makefile (working copy) @@ -0,0 +1,49 @@ +# AEWIN Confidential. Copyright (c) 2015 AEWIN Ltd. http://www.aewin.com.tw + +ifndef TARGET_CPU + TARGET_CPU=$(shell uname -m | sed 's/i.86/i386/' | sed 's/ppc/PPC/' | sed 's/ia64/IA64/') +endif +ifeq ("$(TARGET_CPU)", "PPC") + CFLAGS += -DPOWERPC +endif +ifeq ("$(TARGET_CPU)", "IA64") + CFLAGS += -DKERNEL_64BIT +endif +ifeq ("$(TARGET_CPU)", "PPC64") + CFLAGS += -DKERNEL_64BIT + ifndef USER_BITS + USER_BITS = 64 + endif + CFLAGS += -m$(USER_BITS) + LFLAGS += -m$(USER_BITS) +endif +ifeq ("$(TARGET_CPU)", "x86_64") + CFLAGS += -DKERNEL_64BIT + ifndef USER_BITS + USER_BITS = 64 + endif + CFLAGS += -m$(USER_BITS) + LFLAGS += -m$(USER_BITS) +endif + +TARGET = gpio + +LD = gcc + +OBJS = $(TARGET).o + +$(TARGET) : $(OBJS) + $(LD) -o $@ $(OBJS) $(LFLAGS) + +$(TARGET).o : $(TARGET).c + $(CC) -c $(CFLAGS) -fPIC -o $@ $< + +clean : + rm -f $(OBJS) $(TARGET) + +all: $(TARGET) + +install: + install -Dm 0755 ${.CURDIR}/psu ${ANROOT}/ca/bin/aewin_cb1920/${TARGET} + + Index: /branches/rel_apv_10_7/usr/click/bin/check_mainboard/check_mainboard.c =================================================================== --- /branches/rel_apv_10_7/usr/click/bin/check_mainboard/check_mainboard.c (revision 37953) +++ /branches/rel_apv_10_7/usr/click/bin/check_mainboard/check_mainboard.c (working copy) @@ -93,6 +93,7 @@ #define CHIPSET_ID_HW_FT2004 0x20206000 /*Manufacturer: HANWEI, Product Name: CXH-I16-2000*/ #define CHIPSET_ID_CAR3080 0x00003080 /*CASELL CAR-3080 MB for APV1900/2900*/ #define CHIPSET_ID_CB1924 0x00001924 /*Aewin CB-1924 MB for APV5900*/ +#define CHIPSET_ID_CB1920 0x00001920 /*Aewin CB-1920 MB for APV7900/9900*/ static int @@ -1403,6 +1404,55 @@ } } +// AEWIN CB-1920 supports 2 LEDs. use it as warning LED. +#define AEWIN_CB1920_LED_RUN 0x01 +#define AEWIN_CB1920_LED_WARN 0x02 +#define AEWIN_CB1920_LED_OFF 0x04 /* if set this flag, always set LED off, and do not check run or warn flags. */ + +#define AEWIN_CB1920_SET_RUN_LED_ON_CMD ("/ca/bin/aewin_cb1920/gpio -54l") +#define AEWIN_CB1920_SET_RUN_LED_OFF_CMD ("/ca/bin/aewin_cb1920/gpio -54h") +#define AEWIN_CB1920_SET_WARN_LED_ON_CMD ("/ca/bin/aewin_cb1920/gpio -55l") +#define AEWIN_CB1920_SET_WARN_LED_OFF_CMD ("/ca/bin/aewin_cb1920/gpio -55h") +int +aewin_cb1920_check_led() +{ + int led_status = 0; + size_t len = 0; + + len = sizeof(led_status); + + while (1) { + if (u_sysctlbyname("net.inet.clicktcp.u_cb1920_led_status", (void *)&led_status, (size_t *)&len, NULL, 0) < 0) { + printf("Unable to to get u_cb1920_led_status\n"); + sleep(3); + continue; + } + + if (last_led_status != led_status) { + last_led_status = led_status; + if (led_status & AEWIN_CB1920_LED_OFF) { + /* this flag will be set on system shutdown*/ + system(AEWIN_CB1920_SET_RUN_LED_OFF_CMD); + } + + if (led_status & AEWIN_CB1920_LED_RUN) { + /* this flag will be set on system shutdown*/ + system(AEWIN_CB1920_SET_RUN_LED_ON_CMD); + } else { + /* this flag will be set on system shutdown*/ + system(AEWIN_CB1920_SET_RUN_LED_OFF_CMD); + } + + if (led_status & AEWIN_CB1920_LED_WARN) { + system(AEWIN_CB1920_SET_WARN_LED_ON_CMD); + } else { + system(AEWIN_CB1920_SET_WARN_LED_OFF_CMD); + } + } + usleep(10000); + } +} + /* * Example: * ipmitool sdr type 0x08 -> @@ -1428,6 +1478,15 @@ * PSU0_PIN | 04h | ok | 10.4 | 64 Watts * PSU1_Status | 11h | ok | 10.17 | Presence detected * PSU1_PIN | 14h | ok | 10.20 | 48 Watts + * + * CB-1920 motherboard: + * ipmitool sdr type 0x08 + * PSU 1 Status | 22h | ok | 0.0 | Presence detected + * PSU 1 Pin | 28h | ok | 3.0 | 72 Watts + * PSU 1 Pout | 27h | ok | 3.0 | 64 Watts + * PSU 2 Status | 29h | ok | 0.0 | Presence detected + * PSU 2 Pin | 2Fh | ok | 3.0 | 88 Watts + * PSU 2 Pout | 2Eh | ok | 3.0 | 72 Watts */ static void u_check_power_state_by_ipmi(void) @@ -1466,13 +1525,13 @@ for(i = 0; i < 2; i++) { if (strstr(power_buf[i], "AC lost")) { power_state = (IPMI_DUALPS_OUT | IPMI_QUADWIRE_PS); - if (strstr(power_buf[i], "PS2") || strstr(power_buf[i], "PSU1")) { + if (strstr(power_buf[i], "PS1") || strstr(power_buf[i], "PSU1") || strstr(power_buf[i], "PSU 1")) { power_state |= IPMI_PSMOD_OUT; } goto set_power_state; } else if ((strstr(power_buf[i], "Presence detected") == NULL) || strstr(power_buf[i], "Failure detected")) { power_state = (IPMI_DUALPS_OUT | IPMI_QUADWIRE_PS | IPMI_PSU_AC); - if (strstr(power_buf[i], "PS2") || strstr(power_buf[i], "PSU1")) { + if (strstr(power_buf[i], "PS1") || strstr(power_buf[i], "PSU1") || strstr(power_buf[i], "PSU 1")) { power_state |= IPMI_PSMOD_OUT; } goto set_power_state; @@ -1698,6 +1757,28 @@ u_sysctlbyname("net.inet.clicktcp.u_sys_temp", NULL, 0, (void *)&sys_temp, len); } break; + case CHIPSET_ID_CB1920: + cpu1_temp = u_read_ipmi_sensor("CPU0 Temp"); + if (last_cpu1_temp != cpu1_temp) { + last_cpu1_temp = cpu1_temp; + len = sizeof(cpu1_temp); + u_sysctlbyname("net.inet.clicktcp.u_cpu1_temp", NULL, 0, (void *)&cpu1_temp, len); + } + + cpu2_temp = u_read_ipmi_sensor("CPU1 Temp"); + if (last_cpu2_temp != cpu2_temp) { + last_cpu2_temp = cpu2_temp; + len = sizeof(cpu2_temp); + u_sysctlbyname("net.inet.clicktcp.u_cpu2_temp", NULL, 0, (void *)&cpu2_temp, len); + } + + sys_temp = u_read_ipmi_sensor("System Temp1"); + if (last_sys_temp != sys_temp) { + last_sys_temp = sys_temp; + len = sizeof(sys_temp); + u_sysctlbyname("net.inet.clicktcp.u_sys_temp", NULL, 0, (void *)&sys_temp, len); + } + break; default: break; } @@ -2116,6 +2197,36 @@ } break; + case CHIPSET_ID_CB1920: + fan1_speed = u_read_ipmi_sensor("System Fan1"); + if (last_fan1_speed != fan1_speed) { + last_fan1_speed = fan1_speed; + len = sizeof(fan1_speed); + u_sysctlbyname("net.inet.clicktcp.u_fan1_speed", NULL, 0, (void *)&fan1_speed, len); + } + + fan2_speed = u_read_ipmi_sensor("System Fan2"); + if (last_fan2_speed != fan2_speed) { + last_fan2_speed = fan2_speed; + len = sizeof(fan2_speed); + u_sysctlbyname("net.inet.clicktcp.u_fan2_speed", NULL, 0, (void *)&fan2_speed, len); + } + + fan3_speed = u_read_ipmi_sensor("System Fan3"); + if (last_fan3_speed != fan3_speed) { + last_fan3_speed = fan3_speed; + len = sizeof(fan3_speed); + u_sysctlbyname("net.inet.clicktcp.u_fan3_speed", NULL, 0, (void *)&fan3_speed, len); + } + + fan4_speed = u_read_ipmi_sensor("System Fan4"); + if (last_fan4_speed != fan4_speed) { + last_fan4_speed = fan4_speed; + len = sizeof(fan4_speed); + u_sysctlbyname("net.inet.clicktcp.u_fan4_speed", NULL, 0, (void *)&fan4_speed, len); + } + break; + default: break; } @@ -2352,6 +2463,7 @@ u_chipset_id != CHIPSET_ID_HW_FT2004 && u_chipset_id != CHIPSET_ID_CAR3080 && u_chipset_id != CHIPSET_ID_CB1924 && + u_chipset_id != CHIPSET_ID_CB1920 && u_check_ipmi_device_valid() < 0) { syslog(LOG_ERR, "The ipmi dvice or ipmitool doest not exist.\n"); sleep(600); @@ -2401,6 +2513,11 @@ if(res) { printf("thread_led create err\n"); } + }else if(u_chipset_id == CHIPSET_ID_CB1920) { + res = pthread_create(&thread_led, NULL, (void *)aewin_cb1920_check_led, NULL); + if(res) { + printf("thread_led create err\n"); + } } } Index: /branches/rel_apv_10_7/usr/click/lib/libca_snmp_mib/monitor.c =================================================================== --- /branches/rel_apv_10_7/usr/click/lib/libca_snmp_mib/monitor.c (revision 37953) +++ /branches/rel_apv_10_7/usr/click/lib/libca_snmp_mib/monitor.c (working copy) @@ -41,6 +41,7 @@ #define CHIPSET_ID_HW_FT2004 0x20206000 /*Manufacturer: HANWEI, Product Name: CXH-I16-2000*/ #define CHIPSET_ID_CAR3080 0x00003080 /*CASELL CAR-3080 MB for APV1900/2900*/ #define CHIPSET_ID_CB1924 0x00001924 /*Aewin CB-1924 MB for APV5900*/ +#define CHIPSET_ID_CB1920 0x00001920 /*Aewin CB-1920 MB for APV7900/9900*/ oid monitor_variables_oid[] = { 1,3,6,1,4,1,ARRAY_COMPINFO_MIBOID,32 }; Index: /branches/rel_apv_10_7/usr/click/lib/libip/ipvers.c =================================================================== --- /branches/rel_apv_10_7/usr/click/lib/libip/ipvers.c (revision 37953) +++ /branches/rel_apv_10_7/usr/click/lib/libip/ipvers.c (working copy) @@ -186,6 +186,7 @@ #define CHIPSET_ID_JZD_FT2008 0x20207000 /*JZD D2000*/ #define CHIPSET_ID_CAR3080 0x00003080 /*CASELL CAR-3080 MB for APV1900/2900*/ #define CHIPSET_ID_CB1924 0x00001924 /*Aewin CB-1924 MB for APV5900*/ +#define CHIPSET_ID_CB1920 0x00001920 /*Aewin CB-1920 MB for APV7900/9900*/ #define BUFFER_SIZE 1024 #define QAT_8960_SUBID "0001" #define QAT_8970_SUBID "0002" @@ -397,18 +398,23 @@ chipset_id == CHIPSET_ID_X11SSi_LN4F || chipset_id == CHIPSET_ID_X11DPi_N || chipset_id == CHIPSET_ID_SCB1816 || - chipset_id == CHIPSET_ID_CB1924) { + chipset_id == CHIPSET_ID_CB1924 || + chipset_id == CHIPSET_ID_CB1920) { hw_diag_sprintf_s("%-22s: %d\n", "FAN4 Speed", km_p->fan4_speedr); } - - if (chipset_id == CHIPSET_ID_X9SRW_F || - chipset_id == CHIPSET_ID_X11SSi_LN4F || - chipset_id == CHIPSET_ID_CB2612B || - chipset_id == CHIPSET_ID_SCB1819) { + //Following code snippet looks redundant to me. Comment it out for now + // if (chipset_id == CHIPSET_ID_X9SRW_F || + // chipset_id == CHIPSET_ID_X11SSi_LN4F || + // chipset_id == CHIPSET_ID_CB2612B || + // chipset_id == CHIPSET_ID_SCB1819) { - hw_diag_sprintf_s("%-22s: %d\n", "CPU1 FAN Speed", km_p->cpu1fan_speedr); - } else if (chipset_id != CHIPSET_ID_SCB1816 && chipset_id != CHIPSET_ID_CAR3080 && chipset_id != CHIPSET_ID_CB1924) { + // hw_diag_sprintf_s("%-22s: %d\n", "CPU1 FAN Speed", km_p->cpu1fan_speedr); + // } + if (chipset_id != CHIPSET_ID_SCB1816 && + chipset_id != CHIPSET_ID_CAR3080 && + chipset_id != CHIPSET_ID_CB1924 && + chipset_id != CHIPSET_ID_CB1920) { hw_diag_sprintf_s("%-22s: %d\n", "CPU1 FAN Speed", km_p->cpu1fan_speedr); } Index: /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_host_interface.c =================================================================== --- /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_host_interface.c (revision 37953) +++ /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_host_interface.c (working copy) @@ -240,6 +240,7 @@ #define TM_NCE_MB_MARBLE "Marble" #define TM_NCE_MB_CAR3080 "CAR-3080" #define TM_NCE_MB_CB1924 "CB-1924" +#define TM_NCE_MB_CB1920 "CB-1920" #define CHIPSET_ID_X9SRW_F 0x1d108086 #define CHIPSET_ID_X9DRi_F 0x3c008086 #define CHIPSET_ID_X10DRi 0x2f008086 @@ -260,6 +261,7 @@ #define CHIPSET_ID_JZD_FT2008 0x20207000 /*JZD D2000*/ #define CHIPSET_ID_CAR3080 0x00003080 /*CASELL CAR-3080 MB for APV1900/2900*/ #define CHIPSET_ID_CB1924 0x00001924 /*Aewin CB-1924 MB for APV5900*/ +#define CHIPSET_ID_CB1920 0x00001920 /*Aewin CB-1920 MB for APV7900/9900*/ struct uhi_rte_eal_args atcp_args[] = { {"rte_mem_size", "-m %s", NULL, 0, 1, NULL}, @@ -2641,6 +2643,10 @@ id = CHIPSET_ID_CB1924; goto finished; } + if (strncmp(chipset, TM_NCE_MB_CB1920, strlen(TM_NCE_MB_CB1920)) == 0) { + id = CHIPSET_ID_CB1920; + goto finished; + } } if ( id == 0 ) { Index: /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_host_pci.c =================================================================== --- /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_host_pci.c (revision 37953) +++ /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_host_pci.c (working copy) @@ -11,6 +11,7 @@ #define CHIPSET_ID_HW_FT2004 0x20206000 /*Manufacturer: HANWEI, Product Name: CXH-I16-2000*/ #define CHIPSET_ID_CAR3080 0x00003080 /*CASELL CAR-3080 MB for APV1900/2900*/ #define CHIPSET_ID_CB1924 0x00001924 /*Aewin CB-1924 MB for APV5900*/ +#define CHIPSET_ID_CB1920 0x00001920 /*Aewin CB-1920 MB for APV7900/9900*/ /* pci bridge that present slots */ #define MAX_DEV_PER_CARD 16 @@ -448,6 +449,9 @@ total_pcib = find_pcib(178, NULL, 0); total_pcib += find_pcib(100, NULL, 0); total_pcib += find_pcib(22, NULL, 0); + } else if (chipset_id == CHIPSET_ID_CB1920) { + total_pcib = find_pcib(93, NULL, 0); + total_pcib += find_pcib(23, NULL, 0); } else { /* if there are 2 north bridge, @@ -506,6 +510,9 @@ total_pcib = find_pcib(178, pcib_nicdevs, 0); total_pcib += find_pcib(100, &pcib_nicdevs[total_pcib], 0); total_pcib += find_pcib(22, &pcib_nicdevs[total_pcib], 0); + } else if (chipset_id == CHIPSET_ID_CB1920) { + total_pcib = find_pcib(93, pcib_nicdevs, 0); + total_pcib += find_pcib(23, &pcib_nicdevs[total_pcib], 0); } else { total_pcib = find_pcib(0, pcib_nicdevs, 0); total_pcib += find_pcib(128, &pcib_nicdevs[total_pcib], 1); Index: /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_machdep.c =================================================================== --- /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_machdep.c (revision 37953) +++ /branches/rel_apv_10_7/usr/click/lib/libuinet-atcp/lib/libuinet/uinet_machdep.c (working copy) @@ -1086,6 +1086,10 @@ case AFM_MODEL_5900_APV: ledctl_mode = LEDCTL_NONE; break; + case AFM_MODEL_7900_APV: + case AFM_MODEL_9900_APV: + ledctl_mode = LEDCTL_AEWIN_CB1920; + break; default: ledctl_mode = LEDCTL_SERIAL; break; Index: /branches/rel_apv_10_7/usr/src/sys/click/app/snmp/snmp_trap.c =================================================================== --- /branches/rel_apv_10_7/usr/src/sys/click/app/snmp/snmp_trap.c (revision 37953) +++ /branches/rel_apv_10_7/usr/src/sys/click/app/snmp/snmp_trap.c (working copy) @@ -1632,7 +1632,8 @@ chipset_id == CHIPSET_ID_CB2622 || chipset_id == CHIPSET_ID_CB1727 || chipset_id == CHIPSET_ID_SCB1939 || chipset_id == CHIPSET_ID_MARBLE || chipset_id == CHIPSET_ID_T1SMFT_E4 || chipset_id == CHIPSET_ID_X11SPL_F || chipset_id == CHIPSET_ID_FT2000_4 || chipset_id == CHIPSET_ID_FT2004 || - chipset_id == CHIPSET_ID_HW_FT2004 || chipset_id == CHIPSET_ID_CAR3080 || chipset_id == CHIPSET_ID_CB1924) { + chipset_id == CHIPSET_ID_HW_FT2004 || chipset_id == CHIPSET_ID_CAR3080 || chipset_id == CHIPSET_ID_CB1924 || + chipset_id == CHIPSET_ID_CB1920) { n = u_power_state; } else { n = inb(PW_STATUS) & IPMI_DUALPS_OUT; /*read state of powers from port PW_STATUS*/ Index: /branches/rel_apv_10_7/usr/src/sys/click/net/if_cafw.c =================================================================== --- /branches/rel_apv_10_7/usr/src/sys/click/net/if_cafw.c (revision 37953) +++ /branches/rel_apv_10_7/usr/src/sys/click/net/if_cafw.c (working copy) @@ -393,6 +393,29 @@ }, }; +// AEWIN CB-1920 + +// PCI Bridge 0.0 (0000:17:00.0): 4 NICs found +// PCI Bridge 1.0 (0000:5d:02.0): 4 NICs found +// [root@yv2eM4Xp ca_log]# lspci -vt +// +-[0000:5d]-+-02.0-[5e-61]----00.0-[5f-61]----03.0-[60-61]--+-00.0 Intel Corporation Device 37d3 +// | | +-00.1 Intel Corporation Device 37d3 +// | | +-00.2 Intel Corporation Device 37d3 +// | | \-00.3 Intel Corporation Device 37d3 +// +-[0000:17]-+-00.0-[18-19]--+-00.0 Intel Corporation Ethernet Controller X710 for 10GbE SFP+ +// | | +-00.1 Intel Corporation Ethernet Controller X710 for 10GbE SFP+ +// | | +-00.2 Intel Corporation Ethernet Controller X710 for 10GbE SFP+ +// | | \-00.3 Intel Corporation Ethernet Controller X710 for 10GbE SFP+ +// TODO: Only test 1 add-on NIC. Need add-on NIC options provided from PM +static struct pcib_slot_map nic_slot_map_pcib_CB1920[MAX_SUBMAP][MAX_SLOTS] = { + { + {1, 0}, {-1, -1}, + }, + { + {0, 0}, {-1, -1}, + }, +}; + /* The PCI address for MARBLE onboard NIC is 06:00.0, 06:00.1, 06:00.2, 06:00.3*/ #define MARBLE_ONBOARD_NIC_BUS 6 #define MARBLE_ONBOARD_NIC_DEV 0 @@ -1312,6 +1335,11 @@ map = &nic_slot_map_pcib_CB1924[submap][0]; is_aewin = 1; break; + case CHIPSET_ID_CB1920: + /*all ports sequence are reverse except on board 4x10G X722 SFP+*/ + map = &nic_slot_map_pcib_CB1920[submap][0]; + is_aewin = 1; + break; default: return; } @@ -1549,7 +1577,11 @@ } else if (chipset_id == CHIPSET_ID_CB1924) { add_nics(NICS_ON_BOARD, NIC_ANY_TYPE); add_nics(NICS_ON_SLOTS, NIC_ANY_TYPE); + } else if (chipset_id == CHIPSET_ID_CB1920) { + add_nics(NICS_ON_BOARD, NIC_ANY_TYPE); + add_nics(NICS_ON_SLOTS, NIC_ANY_TYPE); } + n = get_all_nics_on_pcib(); if (clickaddresses->total_nic != n) { @@ -1717,7 +1749,8 @@ chipset_id == CHIPSET_ID_FT2004 || chipset_id == CHIPSET_ID_HW_FT2004 || chipset_id == CHIPSET_ID_CAR3080 || - chipset_id == CHIPSET_ID_CB1924) { /* physical appliances */ + chipset_id == CHIPSET_ID_CB1924 || + chipset_id == CHIPSET_ID_CB1920) { /* physical appliances */ kern_nic_init_by_pcib(); } else if (chipset_id == CHIPSET_ID_CB2622 && (afpacket_interface_count == 1)) { kern_nic_init_by_uinet_for_cb2622(); Index: /branches/rel_apv_10_7/usr/src/sys/click/netinet/click_utils.c =================================================================== --- /branches/rel_apv_10_7/usr/src/sys/click/netinet/click_utils.c (revision 37953) +++ /branches/rel_apv_10_7/usr/src/sys/click/netinet/click_utils.c (working copy) @@ -137,6 +137,7 @@ uint32_t u_apv1880_led_status = 0; uint32_t u_scb1939_led_status = 0; uint32_t u_car3080_led_status = 0; +uint32_t u_cb1920_led_status = 0; SYSCTL_INT(_net_inet_clicktcp, OID_AUTO, u_power_state, CTLFLAG_RW, &u_power_state, 0, ""); @@ -155,6 +156,7 @@ SYSCTL_INT(_net_inet_clicktcp, OID_AUTO, u_apv1880_led_status, CTLFLAG_RW, &u_apv1880_led_status, 0, ""); SYSCTL_INT(_net_inet_clicktcp, OID_AUTO, u_scb1939_led_status, CTLFLAG_RW, &u_scb1939_led_status, 0, ""); SYSCTL_INT(_net_inet_clicktcp, OID_AUTO, u_car3080_led_status, CTLFLAG_RW, &u_car3080_led_status, 0, ""); +SYSCTL_INT(_net_inet_clicktcp, OID_AUTO, u_cb1920_led_status, CTLFLAG_RW, &u_cb1920_led_status, 0, ""); static void dump_mbuf_helper(uint32_t loglevel, struct mbuf *m, int depth); static char *dump_flagnames(uint8_t flags); @@ -1895,6 +1897,27 @@ } } +// AEWIN CB-1920 LED for APV7900/9900 +#define AEWIN1920_LED_RUN 0x01 +#define AEWIN1920_LED_WARN 0x02 + +static void aewin_cb1920_led(int led_mask, int flag) +{ + if (led_mask == AEWIN_LED_RUN) { + if (flag == LED_ON) { + u_cb1920_led_status |= AEWIN1920_LED_RUN; + } else { + u_cb1920_led_status &= ~(AEWIN1920_LED_RUN); + } + } else if (led_mask == AEWIN_LED_WARN) { + if (flag == LED_ON) { + u_cb1920_led_status |= AEWIN1920_LED_WARN; + } else { + u_cb1920_led_status &= ~(AEWIN1920_LED_WARN); + } + } +} + extern int ixgbe_im1316_led(int led_mask, int flag); void led_run(int flag); void led_run(int flag) @@ -1937,6 +1960,10 @@ ledctl_mode = LEDCTL_AEWIN_APV1880; } + if (chipset_id == CHIPSET_ID_CB1920) { + ledctl_mode = LEDCTL_AEWIN_CB1920; + } + /* * Bug 8843, panzj, 2004-09-27 @@ -1970,6 +1997,9 @@ case LEDCTL_MARBLE: marble_led(MARBLE_LED_RUN, flag); break; + case LEDCTL_AEWIN_CB1920: + aewin_cb1920_led(AEWIN_LED_RUN, flag); + break; default: break; } @@ -2020,6 +2050,10 @@ ledctl_mode = LEDCTL_CASWELL_CAR3080; } + if (chipset_id == CHIPSET_ID_CB1920) { + ledctl_mode = LEDCTL_AEWIN_CB1920; + } + /* * Bug 8843, panzj, 2004-09-27 * if model_id is 6,7,8,9 @@ -2054,6 +2088,8 @@ break; case LEDCTL_CASWELL_CAR3080: caswell_car3080_led(CASWELL3080_LED_WARN, flag); + case LEDCTL_AEWIN_CB1920: + aewin_cb1920_led(AEWIN_LED_WARN, flag); default: break; } @@ -2223,7 +2259,8 @@ if (chipset_id == CHIPSET_ID_SCB1816 || chipset_id == CHIPSET_ID_SCB1819 || chipset_id == CHIPSET_ID_CB2612B || chipset_id == CHIPSET_ID_CB2622 || chipset_id == CHIPSET_ID_CB1727 || chipset_id == CHIPSET_ID_SCB1939 || - chipset_id == CHIPSET_ID_CAR3080 || chipset_id == CHIPSET_ID_CB1924) { + chipset_id == CHIPSET_ID_CAR3080 || chipset_id == CHIPSET_ID_CB1924 || + chipset_id == CHIPSET_ID_CB1920) { return check_cpuoverheat_aewin(); } if (chipset_id == CHIPSET_ID_MARBLE) { @@ -4012,6 +4049,46 @@ fan3_state != FAN_FAIL && fan4_state != FAN_FAIL); } +static int +check_fanstop_cb1920(void) +{ + fan1_speed = u_fan1_speed; + clickosmonitor->fan1_speedr = fan1_speed; + if (fan1_speed >= FAN_OK_SPEED) { + fan1_state = FAN_OK; + } else { + fan1_state = FAN_FAIL; + } + + fan2_speed = u_fan2_speed; + clickosmonitor->fan2_speedr = fan2_speed; + if (fan2_speed >= FAN_OK_SPEED) { + fan2_state = FAN_OK; + } else { + fan2_state = FAN_FAIL; + } + + fan3_speed = u_fan3_speed; + clickosmonitor->fan3_speedr = fan3_speed; + if (fan3_speed >= FAN_OK_SPEED) { + fan3_state = FAN_OK; + } else { + fan3_state = FAN_FAIL; + } + + fan4_speed = u_fan4_speed; + clickosmonitor->fan4_speedr = fan4_speed; + if (fan4_speed >= FAN_OK_SPEED) { + fan4_state = FAN_OK; + } else { + fan4_state = FAN_FAIL; + } + + clickosmonitor->chipset_id = CHIPSET_ID_CB1924; + return (fan1_state != FAN_FAIL && fan2_state != FAN_FAIL && + fan3_state != FAN_FAIL && fan4_state != FAN_FAIL); +} + static void get_temp_X8DTH(uint8_t *cpu1_temp, uint8_t *cpu2_temp, uint8_t *sys_temp) @@ -4648,6 +4725,10 @@ return check_fanstop_cb1924(); } + if (chipset_id == CHIPSET_ID_CB1920) { + return check_fanstop_cb1920(); + } + outb(WBIO1, 0x47); n = inb(WBIO2); div1 = 1 << ((n & 0x30) >> 4); @@ -4832,6 +4913,14 @@ clickosmonitor->flagr |= MONITOR_FAN2_SPEED; clickosmonitor->flagr |= MONITOR_FAN3_SPEED; clickosmonitor->flagr |= MONITOR_FAN4_SPEED; + }else if (chipset_id == CHIPSET_ID_CB1920) { + clickosmonitor->flagr |= MONITOR_SYS_TEMP; + clickosmonitor->flagr |= MONITOR_CPU1_TEMP; + clickosmonitor->flagr |= MONITOR_CPU2_TEMP; + clickosmonitor->flagr |= MONITOR_FAN1_SPEED; + clickosmonitor->flagr |= MONITOR_FAN2_SPEED; + clickosmonitor->flagr |= MONITOR_FAN3_SPEED; + clickosmonitor->flagr |= MONITOR_FAN4_SPEED; } } int led_warn_update(void); @@ -5713,7 +5802,8 @@ chipset_id == CHIPSET_ID_SCB1939 || chipset_id == CHIPSET_ID_MARBLE || chipset_id == CHIPSET_ID_CAR3080 || - chipset_id == CHIPSET_ID_CB1924 ||!hardware_control) && + chipset_id == CHIPSET_ID_CB1924 || + chipset_id == CHIPSET_ID_CB1920 ||!hardware_control) && ca_box_no[10] == '0' && ca_box_no[11] == '0' && ca_box_no[12] == '0') { p32 = (unsigned *) &(addr[0]); machigh = ntohs(*p32); Index: /branches/rel_apv_10_7/usr/src/sys/pci/wdt.h =================================================================== --- /branches/rel_apv_10_7/usr/src/sys/pci/wdt.h (revision 37953) +++ /branches/rel_apv_10_7/usr/src/sys/pci/wdt.h (working copy) @@ -205,6 +205,7 @@ LEDCTL_AEWIN_APV1880, LEDCTL_AEWIN_SCB1939, LEDCTL_CASWELL_CAR3080, + LEDCTL_AEWIN_CB1920, }; #define WDT_TICK_SUB(t1, t2) ((int32_t)((uint32_t)(t1)-(uint32_t)(t2))) @@ -245,6 +246,7 @@ #define CHIPSET_ID_JZD_FT2008 0x20207000 /*JZD D2000*/ #define CHIPSET_ID_CAR3080 0x00003080 /*CASELL CAR-3080 MB for APV1900/2900*/ #define CHIPSET_ID_CB1924 0x00001924 /*Aewin CB-1924 MB for APV5900*/ +#define CHIPSET_ID_CB1920 0x00001920 /*Aewin CB-1920 MB for APV7900/9900*/ #define NONARRAYMB "Unknown" @@ -268,6 +270,7 @@ #define APV5200_MB_H8DAE_2 "H8DAE-2" #define TM_NCE_MB_CAR3080 "CAR-3080" #define TM_NCE_MB_CB1924 "CB-1924" +#define TM_NCE_MB_CB1920 "CB-1920" #define MB_SUPPORT_USB(chipset_id) ((chipset_id) == CHIPSET_ID_X8SIE_LN4 || \ (chipset_id) == CHIPSET_ID_X8DTH || \